 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 ?2016 integrated device technology, inc. september 2, 2016 general description the 8V49NS0312 is a clock generator with four output dividers: three integer and one that is either integer or fractional. when used with an external crystal, the 8V49NS0312 generates high perfor- mance timing geared towards the communications and datacom markets, especially for applications demanding extremely low phase noise, such as 10, 40 and 100ge. the 8V49NS0312 provides versatile frequency configurations and output formats and is optimized to deliver excellent phase noise performance. the device delivers an optimum combination of high clock frequency and low phase noise performance, combined with high power supply noise rejection. the 8V49NS0312 supports two types of output levels: lvpecl or lvds on eleven of its outputs. in addition there is a single lvcmos output that has the option of providing a generated clock or acting as a reference bypass output. the device can be configured to deliver specific output configurations under pin control only or additional configurations through an i 2 c serial interface. it is offered in a lead-free (rohs6) 64-pin vfqfn package. features ? eleven differential lvpecl, lvds outputs with programmable voltage swings ? one lvcmos output ? input reference maybe bypassed to this output ? the clock input operates in full differential mode (lvds, lvpecl) or single-ended lvcmos mode ? driven from a crystal or differential clock input ? 2.4-2.5ghz pll frequency range supports ethernet, sonet and cpri frequency plans ? four integer output dividers with a range of output divide ratios (see table 7 ) ? one fractional output divider can generate any desired output frequency ? support of output power-down ? excellent clock output phase noise offset output frequency single-side band phase noise 100khz 156.25mhz -143dbc/hz ? phase noise rms, 156.25mhz, 12khz to 20mhz integration range: 110fs (maximum) ? select configurations may be controlled via the use of control input pins without need for serial port access ? lvcmos compatible i 2 c serial interface gives access to additional configurations either alone or in combination with the control input pins ? single 3.3v supply voltage ? lead-free (rohs 6) 64-pin vfqfn packaging ? -40c to 85c ambient operating temperature femtoclock ? ng clock generator with 4 dividers 8V49NS0312 datasheet
2 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet block diagram figure 1: 8V49NS0312 functional block diagram 3 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet pin assignment nb[0] nb[1] nc[0] nc[1] v cca_in1 na[1] cap bias v cca_in2 cr cap reg lffr lff v cca nc v cc_cp icp 64-pin, 9mm x 9mm vfqfn package lock v cc_sp sclk sdata res na[0] v cca_xt osci osco cap xtal fin[0] fin[1] clk nclk v cc_ck ref_sel v ccob qb0 nqb0 qb1 nqb1 qb2 nqb2 qb3 nqb3 v ccob nd[0] nd[1] v ccod qd1 qd0 nqd0 v ccoa qa0 nqa0 qa1 nqa1 qa2 nqa2 qa3 nqa3 v ccoa v ccoc qc0 nqc0 qc1 nqc1 v ccoc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 8V49NS0312 4 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet pin description and pin characteristic tables table 1: pin descriptions a number name type description 1v ccob power power supply voltage for output bank b (3.3v). 2 qb0 output differential device clock ou tput pair. lvpecl or lvds with configurabl e amplitude. 3 nqb0 output 4 qb1 output differential device clock ou tput pair. lvpecl or lvds with configurabl e amplitude. 5 nqb1 output 6 qb2 output differential device clock ou tput pair. lvpecl or lvds with configurabl e amplitude. 7 nqb2 output 8 qb3 output differential device clock ou tput pair. lvpecl or lvds with configurabl e amplitude. 9 nqb3 output 10 v ccob power power supply voltage for output bank b (3.3v). 11 nd[0] input pullup / pulldown control inputs for output bank d. 3-level signals. refer to table 12 . 12 nd[1] input pullup / pulldown control inputs for output bank d. 3-level signals. refer to table 12 . 13 v ccod power power supply voltage for output bank d (3.3v). 14 qd1 output single-ended output cl ock. lvcmos output levels. 15 qd0 output differential device clock ou tput pair. lvpecl or lvds with configurabl e amplitude. 16 nqd0 output 17 nb[0] input pullup / pulldown control inputs for output bank b. 3-level signals. refer to table 10 . 18 nb[1] input pullup / pulldown control inputs for output bank b. 3-level signals. refer to table 10 . 19 nc[0] input pullup / pulldown control inputs for output bank c. 3-level signals. refer to table 11 . 20 nc[1] input pullup / pulldown control inputs for output bank c. 3-level signals. refer to table 11 . 21 v cca_in1 power analog power supply voltage for pll (3.3v). 22 na[1] input pullup / pulldown control inputs for output bank a. 3-level signals. refer to table 9 . 23 cap bias analog internal vco bias decoupling capacitor. use a 4.7f capacitor between the cap bias terminal and v ee. 24 v cca_in2 power analog power supply voltage for vco (3.3v). 25 cr analog internal vco regulator decoupling capacitor. use a 1f capacitor between the cr and the v cca terminals. 26 cap reg analog internal vco regulator decoupling capacit or. use a 4.7f capacitor between the cap reg terminal and v ee. 5 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet 27 lffr analog ground return path pin for the pll loop filter. 28 lff output loop filter/charge pump output for the femt oclock ng pll. connect to the external loop filter. 29 v cca power analog power supply voltage for vco (3.3v). 30 nc - - no connect. do not use. 31 v cc_cp power analog power supply voltage for pll charge pump (3.3v). 32 icp analog charge pump current input for pll. connect to lff pin (28). 33 v ccoc power power supply voltage for output bank c (3.3v). 34 nqc1 output differential device clock ou tput pair. lvpecl or lvds with configurabl e amplitude. 35 qc1 output 36 nqc0 output differential device clock ou tput pair. lvpecl or lvds with configurabl e amplitude. 37 qc0 output 38 v ccoc power power supply voltage for output bank c (3.3v). 39 v ccoa power power supply voltage for output bank a (3.3v). 40 nqa3 output differential device clock ou tput pair. lvpecl or lvds with configurabl e amplitude. 41 qa3 output 42 nqa2 output differential device clock ou tput pair. lvpecl or lvds with configurabl e amplitude. 43 qa2 output 44 nqa1 output differential device clock ou tput pair. lvpecl or lvds with configurabl e amplitude. 45 qa1 output 46 nqa0 output differential device clock ou tput pair. lvpecl or lvds with configurabl e amplitude. 47 qa0 output 48 v ccoa power power supply voltage for output bank a (3.3v). 49 ref_sel input pulldown selects input reference source. lvcmos interface levels. 0 = crystal input on pins osci, osco (default) 1 = reference clock input on pins clk, nclk 50 v cc_ck power power supply voltage for input clk, nclk (3.3v). 51 nclk input pullup/ pulldown inverting differential clock input. internal resistor bias to v cc_ck. 52 clk input pulldown non-inverting differential clock input. 53 fin[1] input pullup / pulldown control inputs for input reference fr equencies. 3-level signals. refer to table 5 . 54 fin[0] input pullup / pulldown control inputs for input reference fr equencies. 3-level signals. refer to table 5 . 55 cap xtal analog crystal oscillator circuit decoupling capa citor. use a 4.7f capacitor between the cap xtal and the v ee terminals. table 1: pin descriptions a cont. number name type description 6 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 2: input characteristics table 3: output characteristics 56 osco output crystal oscillator interface. 57 osci input crystal oscillator interface. 58 v cca_xt power analog power supply voltage for the crystal oscillator (3.3v). 59 na[0] input pullup / pulldown control inputs for output bank a. 3-level signals. refer to table 9 . 60 res analog connect a 2.8 k ? (1%) resistor to v ee for output current calibration. 61 sdata i/o pullup i 2 c data input/output: lvcmos in terface levels. open drain pin. 62 sclk input pullup i 2 c clock input. lvcmos interface levels. 63 v cc_sp power power supply voltage for the i 2 c port (3.3v). 64 lock output lock status output. lvcmos interface levels. logic low = pll not locked logic high = pll locked epad v ee power negative supply. exposed pad must be connected to ground a. pulldown and pullup refer to internal input resistors. see table 2 , input characteristics, for typical values. symbol parameter test conditio ns minimum typical maximum units c in input capacitance a a. this specification does not apply to osci and osco pins. 3.5 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ? symbol parameter test conditio ns minimum typical maximum units r out output impedance lock v cc a = 3.3v 5% a. v cc denotes v cc_sp, v ccod. 20 ? qd1 30 ? table 1: pin descriptions a cont. number name type description 7 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet principles of operation the 8V49NS0312 can be locked to either an input reference clock or a 10mhz to 50mhz fundamental-mode crystal and generate a wid e range of synchronized output clocks. lock status may be monitored via the lock pin. it could be used for example in either the transmit or receive path of synchronous ethernet or sonet/sdh equipment. the 8V49NS0312 accepts a differential or single-ended input clock ranging from 5mhz up to 1ghz. it generates up to twelve outpu t clocks with up to four different output frequencies, ranging from 10.91mhz up to 2.5ghz. the device outputs are divided into 4 output banks. each bank supports conversion of the input frequency to a different output frequency: one independent or integer-related output frequency on bank d (qd[0:1]) and three more integer-related frequencies on bank a (qa[0: 3]), bank b (qb[0:3]) and bank c (qc[0:1]). all outputs within a bank will have the same frequency. the device is programmable through an i 2 c serial interface or control input pins. pin versus register control the 8V49NS0312 can be configured by the use of input control pins and/or over an i 2 c serial port. the pins / registers used to control each function are shown in table 4 . at power-up, control of each function is via the control input pins. access over the serial port can change each function individually to be controlled by registers. this allows for any mixture of register or pin control. however any of the indicated functions can only be controlled by register or by pin at any given time, not by both. use of register control will allow access to a wid er range of configuration options, but values are lost on power-down. changes to the control input pins while the part is active are allowed, but can not be guaranteed to be glitch-free. it is reco mmended that any such changes be performed by disabling the outputs using the i 2 c-accessible registers, then re-enabling once changes are completed. also, the output dividers, which are synchronized on power-up will not be re-synchronized without an explicit access to the init_clk register bit over the i 2 c interface. any change to the output dividers performed over the i 2 c interface must be followed by an assertion of the init_clk register bit to force the loading of the new divider values, as well as to synchronize the output dividers. table 4: control of specific functions function control select bit control input pins register fields affected prescaler & pll feedback divider fin_ctl fin[1:0] ps[5:0], fdp m[8:0] bank a divider & output type na_ctl na[1:0] na_div, pd_a, en_a, pd_qax, sty_qax, amp_qax[1:0] bank b divider & output type nb_ctl nb[1:0] nb_div, pd_b, en_b, pd_qbx, sty_qbx, amp_qbx[1:0] bank c divider & output type nc_ctl nc[1:0] nc_div, pd_c, en_c, pd_qcx, sty_qcx, amp_qcx[1:0] bank d divider & output type nd_ctl nd[1:0] nd[5:0], nd_fint[3:0], nd_frac[23:0], nd_divf[1:0], nd_src[1:0], pd_d, en_d, pd_qdx, sty_qd0, amp_qd0[1:0] 8 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet input clock selection (ref_sel) the 8V49NS0312 needs to be provided with an input reference frequency either from its crystal input pins (osci, osco) or its re ference clock input pins (clk, nclk). the ref_sel input pin controls which source is used. the crystal input on the 8V49NS0312 is capable of being driven by a parallel-resonant, fundamental mode crystal with a frequenc y of 10mhz to 50mhz. the crystal input also supports being driven by a single-ended crystal oscillator or reference clock, but only a frequency from 10mhz to 50mhz may be used on these pins. the reference clock input accepts clocks with frequencies ranging from 5mhz up to 1ghz. each input can accept lvpecl, lvds, lvh stl, hcsl or lvcmos inputs using 2.5v or 3.3v logic levels as shown in the applications information section of this datasheet. prescaler and pll configuration when the input frequency (f in ), whether generated by a crystal or clock input is known, and the desired pll operating frequency has been determined, several constraints need to be met: ? the phase / frequency detector operating frequency (f pfd ) must be within the specified limits shown in table 28 . this is controlled by selecting an appropriate doubler (fdp) and prescaler (ps) value. if multiple values are possible, a higher f pfd will provide better phase noise performance. ? the vco operating frequency (f vco ) must be within the specified limits shown in table 28 . this is controlled by selecting an appropriate pll feedback divider (m) value. note that it may be necessary to chose a different prescaler value if the limits can not be met by the available values of m. it may also be necessary to select an appropriate input frequency value. several preset configurations may be selected directly from the fin[1:0] control input pins. these configurations are based on a particular input frequency f in and a particular f vco (see table 5 ). these selections apply whether the input frequency is provided from the crystal or reference clock inputs alternatively the user may directly access the registers for m, fdp & ps over the serial interface for a wider range of options . see table 6 for some examples. inputs do not support transmission of spread-spectrum clocking sources. since this family is intended for high-performance appl ications, it will assume input reference sources to have stabilities of + 100ppm or better. table 5: input selection control fin[1] fin[0] f in (mhz) f vco (mhz) high high 38.88 2488.32 high middle a a. a ?middle? voltage level is defined in table 22 . leaving the input pin open will also generate this level via a weak internal resistor network. 38.4 2457.6 high low 31.25 2500 middle high 312.5 2500 middle middle 125 2500 middle low 156.25 2500 low high 100 2500 low middle 25 2500 low low 50 2500 9 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet pll loop bandwidth the 8V49NS0312 uses one external capacitor of fixed value to support its loop bandwidth. a fixed loop bandwidth of approximatel y 200khz is provided. output divider frequency sources output dividers associated with banks a, b & c take their input frequency directly from the pll. bank d also has the option to bypass the input frequency (after mux) directly to the output. table 6: pll frequency control examples f in (mhz) ps fdp f pfd (mhz) m pll operating frequency (mhz) 25 1 2 50 50 2500 39.0625 1 2 78.125 32 2500 50 1 2 100 25 2500 100 1 1 100 25 2500 125 1 1 125 20 2500 156.25 1 1 156.25 16 2500 200 2 1 100 25 2500 250 2 1 125 20 2500 312.5 2 1 156.25 16 2500 400 4 1 100 25 2500 500 4 1 125 20 2500 625 4 1 156.25 16 2500 19.44 1 2 38.88 64 2488.32 38.88 1 2 77.76 32 2488.32 38.4 1 2 76.8 32 2457.6 10 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet integer output dividers (banks a, b, c & d) the 8V49NS0312 supports four integer output dividers: one per output bank. each integer output divider block independently supp orts one of several divide ratios as shown in their respective register descriptions ( table 15 , table 16 , table 17 or table 18 ). select divide ratios can be chosen directly from the control input pins for that particular output bank. the remaining ratios can only be selected via the serial interface. bank d may choose whether to use the integer divider or a separate fractional divider to generate the output. some example output frequencies are shown in table 7 for the minimum f vco (2400mhz), the maximum f vco (2500mhz) and two other common vco frequencies. with appropriate input frequencies and configuration selections, any f vco and f out between the minimum and maximum can be generated. table 7: integer output divider control examples divide ratio f out (mhz) f vco = 2400mhz f vco = 2457.6mhz f vco = 2488.32mhz f vco = 2500mhz 1 2400 2457.6 2488.32 2500 2 1200 1228.8 1244.16 1250 4 600 614.4 622.08 625 5 480 491.52 497.664 500 6 400 409.6 414.72 416.667 8 300 307.2 311.04 318.75 9 266.667 273.07 276.48 277.78 10 240 245.76 248.832 250 12 200 204.8 207.36 208.333 16 150 153.6 155.52 156.25 18 133.333 136.533 138.24 138.889 20 120 122.88 124.416 125 25 96 98.3 99.53 100 32 75 76.8 77.76 78.125 36 66.667 68.267 69.12 69.444 40 60 61.44 62.208 62.5 50 48 49.152 49.766 50 64 37.5 38.4 38.88 39.063 72 33.333 34.133 34.56 34.722 80 30 30.72 31.104 31.25 100 24 24.576 24.883 25 128 18.75 19.2 19.44 19.531 160 15 15.36 15.552 15.625 200 12 12.29 12.44 11.36 220 10.91 11.17 11.31 11.36 11 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet fractional output divider (bank d) for the fractional output divider in bank d, the output divide ratio is given by: where, ? fint = integer part: 5, 6, ...(2 4 -1) - given by nd_fint[3:0] ? frac = fractional part: 0, 1, 2, ...(2 24 -1)- given by nd_frac[23:0] ? fdiv = post-divider: 1, 2 or 4- given by nd_divf[1:0] this provides a frequency range of 20mhz to 312.5mhz. output drivers each of the four output banks are provided with pin or register-controlled output drivers. differential outputs may be individu ally selected as lvds, lvpecl or power-down. when powered down, both outputs of the differential output pair will drive a logic-high level, and the single-ended qd1output will be in hi-z state. the differential outputs may individually choose one of several different output voltage swings: 350mv, 500mv or 750mv, measure d single-ended. note that under pin-control, all differential outputs within an output bank will assume the same configuration. pin-control doe s not allow configuration of individual outputs within a bank. pin control of the output frequencies and protocols see table 8 , table 9 , table 10 , table 11 and table 12 , for pin-control settings. all of the output frequencies assume f vco = 2500mhz. with different f vco configurations, the pins may still be used to select the indicated divide ratios for each bank, but the f out will be different. note that the control pins do not affect the internal register values, but act directly on the output structures. so register v alues will not change to match the control input pin selections. each output bank may be powered-up / down and enabled / disabled by register bits. in the disabled state, an output will drive a logic low level. the default state is all outputs enabled. pin-control does not require register access to enable the outputs. additionally, ind ividual outputs within a bank may be powered up / down. table 8: definition of output disabled / power-down output condition q mn a a. q mn refers to output pins qa[0:3], qb[0:3], qc[0:1] and qd0. nq mn b b. nq mn refers to output pins nqa[0:3], nqb[0:3], nqc[0:1] and nqd0. qd1 disabled (register-control only) low high low power-down (pin-control or register-control) high high hi-z f out f vco 2fint frac 2 24 ---------------- + ?? ?? fdiv ?? ? ? ------------------------------------------------------------------------------ = 12 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 9: bank a divider/ driver pin-control (3-level control signals) na[1] na[0] output type divide ratio f out (mhz) low low lvpecl a 16 156.25 low middle lvpecl 20 125 low high lvpecl 25 100 middle low lvpecl 100 25 middle middle power-down b -- middle high lvds c 16 156.25 high low lvds 20 125 high middle lvds 25 100 high high lvds 50 50 a. under pin control, all outputs of the bank are lvpecl using 750mv output swing. b. no active receivers should be connected to qa outputs . c. under pin control, all outputs of the bank are lvds using 350mv output swing. table 10: bank b divide r/ driver pin-control (3-level control signals) nb[1] nb[0] output type divide ratio f out (mhz) low low lvpecl a 16 156.25 low middle lvpecl 20 125 low high lvpecl 25 100 middle low lvpecl 100 25 middle middle power-down b -- middle high lvds c 16 156.25 high low lvds 20 125 high middle lvds 25 100 high high lvds 50 50 a. under pin control, all outputs of the bank are lvpecl using 750mv output swing. b. no active receivers should be connected to qb outputs . c. under pin control, all outputs of the bank are lvds using 350mv output swing. table 11: bank c divider/ driver pin-control (3-level control signals) nc[1] nc[0] output type divide ratio f out (mhz) low low lvpecl a 8 312.5 low middle lvpecl 16 156.25 low high lvpecl 20 125 middle low lvpecl 100 25 middle middle power-down b - middle high lvds c 20 125 high low lvds 25 100 high middle lvds 50 50 high high lvds 100 25 a. under pin control, all outputs of the bank are lvpecl using 750mv output swing. b. no active receivers should be connected to qc outputs . c. under pin control, all outputs of the bank are lvds using 350mv output swing. table 12: bank d divide r/ driver pin-control (3-level control signals) nd[1] nd[0] qd0 output type qd1 output type divide ratio f out (mhz) low low lvds a a. under pin control, all outputs of the bank are lvds using 350mv output swing. hi-z 25 100 low middle lvds hi-z 50 50 low high lvds hi-z 18.75 b b. generated from fractional divider. 133.333 middle low lvds hi-z 37.5 b 66.667 middle middle power-down c c. no active receivers should be connected to qd0 output. hi-z - - middle high power-down c lvcmos 75 33.333 high low lvds hi-z 100 25 high middle lvds hi-z 20 125 high high lvds lvcmos 1 f in d d. this bypasses the input frequency directly to the output. 13 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet device start-up & reset behavior the 8V49NS0312 has an internal power-on reset (por) circuit.the por circuit will remain active for a maximum of 175msec after d evice power-up. while in the reset state (por active), the device will operate as follows: ? all registers will return to & be held in their default states as indicated in the applicable register description. ? all internal state machines will be in their reset conditions. ? the serial interface will not respond to read or write cycles. ? all clock outputs will be enabled. ? lock status will be cleared. upon the internal por circuit expiring, the device will exit reset and begin self-configuration. self-configuration will consist of loading appropriate default values into each register as indicated by the control input pins and the defaults indicated in the register descriptions. once the full configuration has been loaded, the device will respond to accesses on the serial port and will attempt to lock th e pll to the input frequency and begin operation. once the pll is locked, all the outputs derived from it will be synchronized. 14 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet serial control port description serial control port configuration description the device has a serial control port capable of responding as a slave in an i 2 c compatible configuration at a base address of 1101100b, to allow access to any of the internal registers for device programming or examination of internal status. all registers are configured to have default values. see the specifics for each register for details. default values for regist ers will be set after reset by the configuration pins. any changes to the configuration pins will result in the appropriate register(s) being changed to reflect the new pin-controlle d setup. any such change while the part is operating may result in glitches on output clocks, even if those particular clocks are not being recon figured. i 2 c mode operation the i 2 c interface is designed to fully support v1.2 of the i 2 c specification for normal and fast mode operation. the device acts as a slave device on the i 2 c bus at 100khz or 400khz using a fixed base address of 1101100b. the interface accepts byte-oriented block write and block read operations. one address byte specifies the register address of the byte position of the first register to write or read. d ata bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). read and write block transfe rs can be stopped after any complete byte transfer. during a write operation, data will not be moved into the registers until the stop bit is rec eived, at which point, all data received in the block write will be written simultaneously. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resistors have a size of 51k ? typical. figure 2: i 2 c slave read and write cycle sequencing current read s dev addr + r a data x a data x +1 a a data n a p sequential read s dev addr + w a data x a data x +1 a a data n a p offset addr x a sr dev addr + r a sequential write s dev addr + w a data x p a data x +1 a a data n a offset addr x a s = start sr = repeated start a = acknowledge a = non-acknowledge p = stop note: data x refers to the data at offset addr x, data x+1 refers to the data at offset addr +1, etc. from master to slave from slave to master 15 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet register description table 13: register blocks register ranges offset (hex) register block description 00 - 08 prescaler & pll control registers 09 - 0f reserved a a. reserved registers should not be written to and have indeterminate read values. 10 - 17 bank a control registers 18 - 1f bank b control registers 20 - 27 bank c control registers 28 - 31 bank d control registers 32 - 37 reserved 38 - 3c reserved 3d - 40 device control registers 41 - 4b reserved 4c - 4f reserved 50 - ff reserved 16 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 14: prescaler & pll control register bit field locations and descriptions prescaler & pll cont rol register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 00 rsvd rsvd ps[5:0] 01 rsvd fdp 02 rsvd fin_ctl osc_low 03 rsvd 04 rsvd m[8] 05 m[7:0] 06 rsvd 07 rsvd 08 rsvd cp[4:0] prescaler & pll control register block field descriptions bit field name field type default value description ps[5:0] r/w 000000b prescaler - scales input frequency by the value: 00h = reserved 01h - 7fh = divide by the value used (e.g. 04 = divide-by-4) fdp r/w 1b input frequency doubler: 0 = disabled 1 = enabled fin_ctl r/w 0b prescaler and pll configuration control: 0 = ps[5:0], fdp and m settings dete rmined by fin[1:0] control pins 1 = ps[5:0], fdp and m settings determined by register settings over i 2 c osc_low r/w 0b crystal oscillator gain control selection: 0 = normal gain for crystal frequencies of 25mhz and up 1 = low gain for crystal frequencies less than 25mhz m[8:0] r/w 019h pll feedback divider ratio: 000h - 003h = reserved (do not use) 004h - 1ffh = divide f vco by the value cp[4:0] r/w 11001b pll charge pump current control: i cp = 200 a x (cp[4:0] + 1). max. charge pump current is 6.4 ma. de fault setting is 5.2ma: ((25+1) x 200 a). rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. 17 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 15: bank a control register bit field locations and descriptions bank a control register block field locations address (hex)d7d6d5d4d3d2 d1 d0 10 rsvd na[5:0] 11 rsvd 12 pd_a rsvd na_ctl 13 rsvd 14 pd_qa0 rsvd sty_qa0 amp_qa0[1:0] 15 pd_qa1 rsvd sty_qa1 amp_qa1[1:0] 16 pd_qa2 rsvd sty_qa2 amp_qa2[1:0] 17 pd_qa3 rsvd sty_qa3 amp_qa3[1:0] bank a control register block field descriptions bit field name field type default value description na[5:0] r/w 0dh divider ratio for bank a: any changes made to this register will not ta ke effect until the init_clk register bit is toggled. 00 0000b = reserved 00 0001b = 1 00 0010b = 2 00 0011b = 3 00 0100b = 4 00 0101b = 5 00 0110b = 6 00 0111b = 8 00 1000b = 9 00 1001b = 10 00 1010b = 12 00 1011b = 14 00 1100b = 15 00 1101b = 16 00 1110b = 18 00 1111b = 20 01 0000b = 21 01 0001b = 22 01 0010b = 24 01 0011b = 25 01 0100b = 27 01 0101b = 28 01 0110b = 30 01 0111b = 32 01 1000b = 33 01 1001b = 35 01 1010b = 36 01 1011b = 40 01 1100b = 42 01 1101b = 44 01 1110b = 45 01 1111b = 48 10 0000b = 50 10 0001b = 54 10 0010b = 55 10 0011b = 56 10 0100b = 60 10 0101b = 64 10 0110b = 66 10 0111b = 70 10 1000b = 72 10 1001b = 80 10 1010b = 84 10 1011b = 88 10 1100b = 90 10 1101b = 96 10 1110b = 100 10 1111b = 108 11 0000b = 110 11 0001b = 112 11 0010b = 120 11 0011b = 128 11 0100b = 132 11 0101b = 140 11 0110b = 144 11 0111b = 160 11 1000b = 176 11 1001b = 180 11 1010b = 200 11 1011b = 220 11 1100b = reserved 11 1101b = reserved 11 1110b = reserved 11 1111b = reserved pd_a r/w 0b power-down bank a: 0 = bank a & all qa outputs powered and operate normally 1 = bank a & all qa outputs powered-down - no active receivers should be connected to qa outputs. when powering-down the out put bank, it is recommended to also write a ?1? to the pd_qax registers. na_ctl r/w 0b bank a configuration control: 0 = na[5:0], pd_a, en_a, sty_ax and amp_ax[1:0] settings determined by na[1:0] control pins 1 = na[5:0], pd_a, en_a, sty_ax and amp_ ax[1:0] settings determined by register settings over i 2 c pd_qax r/w 0b power-down output qax: 0 = qax output powered and operates normally 1 = qax output powered-down - no active receivers should be connected to the qax output 18 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet sty_qax r/w 0b output style for output qax: 0 = qax is lvds 1 = qax is lvpecl amp_qax[1:0] r/w 00b output amplitude for output qax (measured single-ended): 00 = 350mv 01 = 500mv 10 = 750mv 11 = reserved rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. bank a control register block field descriptions bit field name field type default value description 19 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 16: bank b control register bit field locations and descriptions bank b control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 18 rsvd nb[5:0] 19 rsvd 1a pd_b rsvd nb_ctl 1b rsvd 1c pd_qb0 rsvd sty_qb0 amp_qb0[1:0] 1d pd_qb1 rsvd sty_qb1 amp_qb1[1:0] 1e pd_qb2 rsvd sty_qb2 amp_qb2[1:0] 1f pd_qb3 rsvd sty_qb3 amp_qb3[1:0] bank b control register block field descriptions bit field name field type default value description nb[5:0] r/w 0dh divider ratio for bank b: any changes made to this register will not take effect until the init_clk register bit is toggled. 00 0000b = reserved 00 0001b = 1 00 0010b = 2 00 0011b = 3 00 0100b = 4 00 0101b = 5 00 0110b = 6 00 0111b = 8 00 1000b = 9 00 1001b = 10 00 1010b = 12 00 1011b = 14 00 1100b = 15 00 1101b = 16 00 1110b = 18 00 1111b = 20 01 0000b = 21 01 0001b = 22 01 0010b = 24 01 0011b = 25 01 0100b = 27 01 0101b = 28 01 0110b = 30 01 0111b = 32 01 1000b = 33 01 1001b = 35 01 1010b = 36 01 1011b = 40 01 1100b = 42 01 1101b = 44 01 1110b = 45 01 1111b = 48 10 0000b = 50 10 0001b = 54 10 0010b = 55 10 0011b = 56 10 0100b = 60 10 0101b = 64 10 0110b = 66 10 0111b = 70 10 1000b = 72 10 1001b = 80 10 1010b = 84 10 1011b = 88 10 1100b = 90 10 1101b = 96 10 1110b = 100 10 1111b = 108 11 0000b = 110 11 0001b = 112 11 0010b = 120 11 0011b = 128 11 0100b = 132 11 0101b = 140 11 0110b = 144 11 0111b = 160 11 1000b = 176 11 1001b = 180 11 1010b = 200 11 1011b = 220 11 1100b = reserved 11 1101b = reserved 11 1110b = reserved 11 1111b = reserved pd_b r/w 0b power-down bank b: 0 = bank b & all qb outputs powered and operate normally 1 = bank b & all qb outputs powered-down - no active receivers should be connected to qb outputs nb_ctl r/w 0b bank a configuration control: 0 = nb[5:0], pd_b, en_b, sty_bx and amp_bx[1:0] settings determined by nb[1:0] control pins 1 = nb[5:0], pd_b, en_b, sty_bx and amp_ bx[1:0] settings determined by register settings over i 2 c pd_qbx r/w 0b power-down output qbx: 0 = qbx output powered and operates normally 1 = qbx output powered-down - no active receivers should be connected to the qbx output. when powering-down the output bank, it is recommended to also write a ?1? to the pd_qbx registers. 20 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet sty_qbx r/w 0b output style for output qbx: 0 = qbx is lvds 1 = qbx is lvpecl amp_qbx[1:0] r/w 00b output amplitude for output qbx (measured single-ended): 00 = 350mv 01 = 500mv 10 = 750mv 11 = reserved rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. bank b control register block field descriptions bit field name field type default value description 21 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 17: bank c control register bit field locations and descriptions bank c control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 20 rsvd nc[5:0] 21 rsvd 22 pd_c rsvd nc_ctl 23 rsvd 24 pd_qc0 rsvd sty_qc0 amp_qc0[1:0] 25 pd_qc1 rsvd sty_qc1 amp_qc1[1:0] 26 rsvd 27 rsvd bank c control register block field descriptions bit field name field type default value description nc[5:0] r/w 0dh divider ratio for bank c: any changes made to this register will not take effect until the init_clk register bit is toggled. 00 0000b = reserved 00 0001b = 1 00 0010b = 2 00 0011b = 3 00 0100b = 4 00 0101b = 5 00 0110b = 6 00 0111b = 8 00 1000b = 9 00 1001b = 10 00 1010b = 12 00 1011b = 14 00 1100b = 15 00 1101b = 16 00 1110b = 18 00 1111b = 20 01 0000b = 21 01 0001b = 22 01 0010b = 24 01 0011b = 25 01 0100b = 27 01 0101b = 28 01 0110b = 30 01 0111b = 32 01 1000b = 33 01 1001b = 35 01 1010b = 36 01 1011b = 40 01 1100b = 42 01 1101b = 44 01 1110b = 45 01 1111b = 48 10 0000b = 50 10 0001b = 54 10 0010b = 55 10 0011b = 56 10 0100b = 60 10 0101b = 64 10 0110b = 66 10 0111b = 70 10 1000b = 72 10 1001b = 80 10 1010b = 84 10 1011b = 88 10 1100b = 90 10 1101b = 96 10 1110b = 100 10 1111b = 108 11 0000b = 110 11 0001b = 112 11 0010b = 120 11 0011b = 128 11 0100b = 132 11 0101b = 140 11 0110b = 144 11 0111b = 160 11 1000b = 176 11 1001b = 180 11 1010b = 200 11 1011b = 220 11 1100b = reserved 11 1101b = reserved 11 1110b = reserved 11 1111b = reserved pd_c r/w 0b power-down bank c: 0 = bank c & all qc outputs powered and operate normally 1 = bank c & all qc outputs powered-down - no active receivers should be connected to qc outputs nc_ctl r/w 0b bank c configuration control: 0 = nc[5:0], pd_c, en_c, st y_cx and amp_cx[1:0] settings determined by nc[1:0] control pins 1 = nc[5:0], pd_c, en_c, sty_cx and amp_cx [1:0] settings determined by register settings over i 2 c pd_qcx r/w 0b power-down output qcx: 0 = qcx output powered and operates normally 1 = qcx output powered-down - no active receivers should be connected to the qcx output. when powering-down the output bank, it is recommended to also write a ?1? to the pd_qcx registers. 22 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet sty_qcx r/w 0b output style for output qcx: 0 = qcx is lvds 1 = qcx is lvpecl amp_qcx[1:0] r/w 00b output amplitude for output qcx (measured single-ended): 00 = 350mv 01 = 500mv 10 = 750mv 11 = reserved rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. bank c control register block field descriptions bit field name field type default value description 23 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 18: bank d control register bit field locations and descriptions bank d control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 28 nd_frac[7:0] 29 nd_frac[15:8] 2a nd_frac[23:16] 2b rsvd nd_fint[3:0] 2c rsvd nd[5:0] 2d rsvd nd_divf[1:0] nd_div nd_src 2e pd_d rsvd nd_ctl 2f rsvd 30 pd_qd0 rsvd sty_qd0 amp_qd0[1:0] 31 pd_qd1 rsvd bank d control register block field descriptions bit field name field type default value description nd_frac[23:0] r/w 600000h fractional portion of divider ratio for fractional divider for bank d: fraction used in divide ratio = nd_frac[23:0] / 2 24 nd_fint[3:0] r/w 1001b integer portion of divider ratio for fractional divider for bank d: 0h - 4h= reserved 5h - fh = divide by the value used (e.g. 5 = divide-by-5) nd[5:0] r/w 0dh divider ratio for bank d: any changes made to this register will not take effect until the init_clk register bit is toggled. 00 0000b = reserved 00 0001b = 1 00 0010b = 2 00 0011b = 3 00 0100b = 4 00 0101b = 5 00 0110b = 6 00 0111b = 8 00 1000b = 9 00 1001b = 10 00 1010b = 12 00 1011b = 14 00 1100b = 15 00 1101b = 16 00 1110b = 18 00 1111b = 20 01 0000b = 21 01 0001b = 22 01 0010b = 24 01 0011b = 25 01 0100b = 27 01 0101b = 28 01 0110b = 30 01 0111b = 32 01 1000b = 33 01 1001b = 35 01 1010b = 36 01 1011b = 40 01 1100b = 42 01 1101b = 44 01 1110b = 45 01 1111b = 48 10 0000b = 50 10 0001b = 54 10 0010b = 55 10 0011b = 56 10 0100b = 60 10 0101b = 64 10 0110b = 66 10 0111b = 70 10 1000b = 72 10 1001b = 80 10 1010b = 84 10 1011b = 88 10 1100b = 90 10 1101b = 96 10 1110b = 100 10 1111b = 108 11 0000b = 110 11 0001b = 112 11 0010b = 120 11 0011b = 128 11 0100b = 132 11 0101b = 140 11 0110b = 144 11 0111b = 160 11 1000b = 176 11 1001b = 180 11 1010b = 200 11 1011b = 220 11 1100b = reserved 11 1101b = reserved 11 1110b = reserved 11 1111b = reserved note: qd1 cmos output should be powered- off or disabled for output frequencies greater than the maximum listed for it in table 28 . nd_divf[1:0] r/w 00b post-divider ratio for fractional divider for bank d: 00 = 1 01 = 2 10 = 4 11 = reserved 24 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet nd_div r/w 0b control which divider is used to provide output frequency for bank d: 0 = integer divider d (nd configures this) 1 = fractional mode (nd_fint, nd_frac and nd_divf configure this) nd_src r/w 0b output source selection for bank d: 0 = bank d is driven from the integer or fractional divider as selected by nd_src 1 = bank d is driven from the input reference (after the mux) with f in pd_d r/w 0b power-down bank d: 0 = bank d & all qd outputs powered and operate normally 1 = bank d & all qd outputs powered-down - no active receivers should be connected to qd0 output. qd1 output is in high-impedance. nd_ctl r/w 0b bank d configuration control: 0 = nd[5:0], nd_frac[23:0 ], nd_fint[3:0], nd_divf[ 1:0], nd_div, nd_src, pd_d, en_d, sty_d0 and amp_d0[1:0] settings determined by nd[1:0] control pins 1 = nd[5:0], nd_frac[23:0 ], nd_fint[3:0], nd_divf[ 1:0], nd_div, nd_src, pd_d, en_d, sty_d0 and amp_d0[1:0] settings determined by register settings over i 2 c pd_qdx r/w 0b power-down output qdx: 0 = qd[0:1] outputs powered and operate normally 1 = qd0 output powered-down - no active re ceivers should be connected to the qd0 output, qd1 output is in high-impedance. when powering-down the output bank, it is recommended to also write a ?1? to the pd_qdx registers. sty_qd0 r/w 0b output style for output qd0: 0 = qd0 is lvds 1 = qd0 is lvpecl amp_qd0[1:0] r/w 00b output amplitude for output qd0 (measured single-ended): 00 = 350mv 01 = 500mv 10 = 750mv 11 = reserved rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. bank d control register block field descriptions bit field name field type default value description 25 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 19: device control register bit field locations and descriptions device control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 3d init_clk rsvd 3e relock rsvd 3f pb_cal rsvd 40 rsvd en_a en_b en_c en_d device control register block field descriptions bit field name field type default value description init_clk w/o a 0b writing a ?1? to this bit location will cause output dividers to be synchronized. must be done every time a divider value is changed if output divider synchronization is desired. this bit will auto-clear after output divider synchronization is completed. relock w/o a 0b writing a ?1? to this bit location will cause the pll to re-lock. this bit will auto-clear. pb_cal w/o a 0b precision bias calibration: setting this bit to 1 will start the calibration of an internal precision bias current source. the bias current is used as reference fo r outputs configured as lvds and for as reference for the charge pump currents. this bit will auto-clear after the calibration is completed. en_a r/w 1b output enable control for bank a: 0 = bank a outputs qa[0:3] disabled to logic-low state (qax = 0, nqax = 1) 1 = bank a outputs qa[0:3] enabled en_b r/w 1b output enable control for bank b: 0 = bank b outputs qb[0:3] disabled to logic-low state (qbx = 0, nqbx = 1) 1 = bank b outputs qb[0:3] enabled en_c r/w 1b output enable control for bank c: 0 = bank c outputs qc[0:1] disabled to logic-low state (qcx = 0, nqcx = 1) 1 = bank c outputs qc[0:1] enabled en_d r/w 1b output enable control for bank d: 0 = bank d outputs qd[0:1] disabled to logi c-low state (qd0 = 0, nqd0 = 1, qd1 = 0) note that if bank d is powered down via the pd_d bit or the qd1 output is powered down by the pd_qd1 bit, then qd1 will be in high-impedance regardless of the state of this bit. 1 = bank d outputs qd[0:1] enabled rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. a. these bits are read as ?0?. when a ?1? is written to them, it will have the indicated effect and then self-clear back to ?0? . 26 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of the product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. table 20: absolute maximum ratings item rating supply voltage, v cc 3.6v inputs, v i osci other inputs -0.5v to 3.6v -0.5v to 3.6v outputs, v o (lvcmos) -0.5v to 3.6v outputs, i o (lvpecl) continuous current surge current 50ma 100ma outputs, i o (lvds) continuous current surge current 50ma 100ma maximum junction temperature, t jmax 125 ? c storage temperature, t stg -65 ? c to 150 ? c 27 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet dc electrical characteristics table 21: power supply dc characteristics, v cc_x a = v ccox b = 3.3v5%, t a = -40c to +85c, v ee = 0v, symbol parameter test conditio ns minimum typical maximum units v cc_x core supply voltage 3.135 3.3 3.465 v v cca_x c analog supply voltage 3.135 3.3 3.465 v v ccox output supply voltage 3.135 3.3 3.465 v i cc_x d core supply current lvpecl all outputs enabled & terminated e 73 100 ma lvds all outputs enabled & terminated f 73 100 ma i cca_x g analog supply current lvpecl all outputs enabled & terminated e 141 169 ma lvds all outputs enabled & terminated f 141 167 ma i ccoa h bank a output supply current lvpecl 350mv, outputs enabled & terminated e 189 226 ma 500mv, outputs enabled & terminated e 183 217 ma 750mv, outputs enabled & terminated e 172 205 ma lvds 350mv, outputs enabled & terminated f 84 103 ma 500mv, outputs enabled & terminated f 101 124 ma 750mv, outputs enabled & terminated f 130 161 ma lvpecl 350mv, outputs disabled & unterminated 8 10 ma 500mv, outputs disabled & unterminated 10 12 ma 750mv, outputs disabled & unterminated 12 15 ma lvds 350mv, outputs disabled & unterminated 26 32 ma 500mv, outputs disabled & unterminated 36 43 ma 750mv, outputs disabled & unterminated 51 62 ma 28 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet i ccob h bank b output supply current lvpecl 350mv, outputs enabled & terminated e 196 234 ma 500mv, outputs enabled & terminated e 188 224 ma 750mv, outputs enabled & terminated e 177 211 ma lvds 350mv, outputs enabled & terminated f 86 105 ma 500mv, outputs enabled & terminated f 103 126 ma 750mv, outputs enabled & terminated f 132 163 ma lvpecl 350mv, outputs disabled & unterminated 9 11 ma 500mv, outputs disabled & unterminated 10 13 ma 750mv, outputs disabled & unterminated 13 16 ma lvds 350mv, outputs disabled & unterminated 27 33 ma 500mv, outputs disabled & unterminated 36 44 ma 750mv, outputs disabled & unterminated 52 62 ma i ccoc h bank c output supply current lvpecl 350mv, outputs enabled & terminated e 109 131 ma 500mv, outputs enabled & terminated e 106 127 ma 750mv, outputs enabled & terminated e 100 120 ma lvds 350mv, outputs enabled & terminated f 55 67 ma 500mv, outputs enabled & terminated f 64 78 ma 750mv, outputs enabled & terminated f 78 95 ma lvpecl 350mv, outputs disabled & unterminated 1 2 ma 500mv, outputs disabled & unterminated 1 2 ma 750mv, outputs disabled & unterminated 1 2 ma lvds 350mv, outputs disabled & unterminated 1 2 ma 500mv, outputs disabled & unterminated 1 2 ma 750mv, outputs disabled & unterminated 1 2 ma table 21: power supply dc characteristics, v cc_x a = v ccox b = 3.3v5%, t a = -40c to +85c, v ee = 0v, cont. symbol parameter test conditio ns minimum typical maximum units 29 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet i ccod h bank d output supply current lvpecl 350mv, outputs enabled & terminated e 91 114 ma 500mv, outputs enabled & terminated e 89 112 ma 750mv, outputs enabled & terminated e 86 109 ma lvds 350mv, outputs enabled & terminated f 57 69 ma 500mv, outputs enabled & terminated f 62 75 ma 750mv, outputs enabled & terminated f 70 85 ma lvpecl 350mv, outputs disabled & unterminated 3 5 ma 500mv, outputs disabled & unterminated 3 5 ma 750mv, outputs disabled & unterminated 3 5 ma lvds 350mv, outputs disabled & unterminated 3 5 ma 500mv, outputs disabled & unterminated 3 5 ma 750mv, outputs disabled & unterminated 3 5 ma i ee h power supply current for v ee lvpecl 350mv, outputs enabled & terminated e 385 470 ma 500mv, outputs enabled & terminated e 394 481 ma 750mv, outputs enabled & terminated e 407 497 ma lvpecl 350mv, outputs disabled & unterminated 233 277 ma 500mv, outputs disabled & unterminated 236 280 ma 750mv, outputs disabled & unterminated 241 286 ma a. v cc_x denotes v cc_cp, v cc_ck, v cc_sp. b. v ccox denotes v ccoa, v ccob, v ccoc, v ccod. c. v cca_x denotes v cca_in1, v cca_in2, v cca, v cca_xt. d. i cc_x denotes i cc_cp, i cc_ck, i cc_sp. e. differential outputs terminated 50 ? to v ccox - 2v. qd1 output terminated 50 ?? to v ccod /2. f. differential outputs terminated 100 ? across q and nq. qd1 output terminated 50 ?? to v ccod /2. g. i cca_x denotes i cca_in1, i cca_in2, i cca, i cca_xt. h. internal maximum dynamic switching current is included. table 21: power supply dc characteristics, v cc_x a = v ccox b = 3.3v5%, t a = -40c to +85c, v ee = 0v, cont. symbol parameter test conditio ns minimum typical maximum units 30 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 22: lvcmos dc characteristics for 3-level pins, v cc_x a = v ccox b = 3.3v5%, t a = -40c to +85c, v ee = 0v symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 0.7 * v cc c 3.465 v v im input middle voltage fin[1:0], na[1:0], nb[1:0], nc[1:0], nd[1:0] 0.4 * v cc c 0.6 * v cc c v v il input low voltage -0.3 0.3 * v cc c v i ih input high current fin[1:0], na[1:0], nb[1:0], nc[1:0], nd[1:0] v cc c = v in = 3.465v 150 a i im input middle current fin[1:0], na[1:0], nb[1:0], nc[1:0], nd[1:0] v in = v cc c / 2 1 a i il input low current fin[1:0], na[1:0], nb[1:0], nc[1:0], nd[1:0] v cc c = 3.465v, v in = 0v -150 a a. v cc_x denotes v cc_cp, v cc_ck, v cc_sp. b. v ccox denotes v ccoa, v ccob, v ccoc, v ccod. c. v cc denotes v cca_in1, v cc_ck. table 23: lvcmos dc characteristics for 2-level pins, v cc_x a = v ccox b = 3.3v5%, t a = -40c to +85c, v ee = 0v a. v cc_x denotes v cc_cp, v cc_ck, v cc_sp. b. v ccox denotes v ccoa, v ccob, v ccoc, v ccod. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 0.7 * v cc c c. v cc denotes v cc_ck. 3.465 v v il input low voltage ref_sel -0.3 0.3 * v cc c v sdata, sclk -0.3 0.15 * v cc c v i ih input high current sclk, sdata v cc c = v in = 3.465v 5 a ref_sel v cc c = v in = 3.465v 150 a i il input low current sclk, sdata v cc c = 3.465v, v in = 0v -150 a ref_sel v cc c = 3.465v, v in = 0v -5 a v oh output high voltage lock i oh = -4ma 2.2 v v ol output low voltage sdata, lock i ol = 4ma 0.45 v 31 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 24: differential input dc characteristics, v cc_x a = v ccox b = 3.3v5%, t a = -40c to +85c, v ee = 0v symbol parameter test conditions minimum typical maximum units i ih input high current clk_in, nclk_in v cc c = v in = 3.465v 150 a i il input low current clk_in v cc c = 3.465v, v in = 0v -5 a nclk_in v cc c = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage d, e clk_in, nclk_in 0.2 1.4 v v cmr common mode input voltage d, e clk_in, nclk_in v ee + 1.1 v cc c ? 0.3 v a. v cc_x denotes v cc_cp, v cc_ck, v cc_sp. b. v ccox denotes v ccoa, v ccob, v ccoc, v ccod. c. v cc denotes v cc_ck. d. common mode voltage is defined as the cross point. e. input voltage cannot be less than v ee - 300mv or more than v cc. table 25: lvpecl output dc characteristics (qmn a ), v cc_x b = v ccox c = 3.3v5%, t a = -40c to +85c, v ee = 0v a. in this table, qmn denotes the differential outputs qa[0:3], qb[0:3], qc[0:1] or qd0. note that qd1 is not included because it is not differential. b. v cc_x denotes v cc_cp, v cc_ck, v cc_sp. c. v ccox denotes v ccoa, v ccob, v ccoc, v ccod. symbol parameter test conditio ns minimum typical maximum units v oh output high voltage d d. outputs terminated with 50 ? to v ccox ? 2v. 350mv amplitude setting v ccox ? 1.1 v ccox ? 0.8 v 500mv amplitude setting v ccox ? 1.1 v ccox ? 0.8 750mv amplitude setting v ccox ? 1.1 v ccox ? 0.8 v ol output low voltage d 350mv amplitude setting v ccox ? 1.5 v ccox ? 1.1 v 500mv amplitude setting v ccox ? 1.6 v ccox ? 1.3 750mv amplitude setting v ccox ? 1.8 v ccox ? 1.5 v swing single-ended peak-to-peak output voltage swing 350mv amplitude setting 280 350 420 mv 500mv amplitude setting 430 500 570 750mv amplitude setting 630 700 770 32 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 26: lvds output dc characteristics (qmn a ), v cc_x b = v ccox c = 3.3v5%, t a = -40c to +85c, v ee = 0v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 350mv amplitude setting 0.27 0.32 0.37 v 500mv amplitude setting 0.39 0.46 0.53 750mv amplitude setting 0.62 0.69 0.76 ? v od v od magnitude change 50 mv v os offset voltage d, e, f 350mv amplitude setting 1.9 2.3 2.7 v 500mv amplitude setting 1.8 2.2 2.6 750mv amplitude setting 1.7 2.1 2.5 ? v os v os magnitude change 50 mv a. in this table, qmn denotes the differential outputs qa[0:3], qb[0:3], qc[0:1] or qd0. note that qd1 is not included because it is not differential. b. v cc_x denotes v cc_cp, v cc_ck, v cc_sp. c. v ccox denotes v ccoa, v ccob, v ccoc, v ccod. d. no external dc pulldown resistor. e. loading condition is with 100 ? across the differential output. f. offset voltage (v os ) changes with supply voltage v ccox. table 27: crystal characteristics parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 10 50 mhz equivalent series resistance (esr) c l = 12pf 60 ? c l = 18pf 15 30 ? load capacitance (c l ) 12 pf maximum crystal drive level 200 ? w frequency stability (total) -100 100 ppm 33 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet ac electrical characteristics table 28: ac characteristics, a v cc_x b = v ccox c = 3.3v+5%, t a = -40c to +85c, v ee = 0v a. electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the d evice is mounted in a test socket with main- tained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. b. v cc_x denotes v cc_cp, v cc_ck, v cc_sp. c. v ccox denotes v ccoa, v ccob, v ccoc, v ccod. symbol parameter test conditio ns minimum typical maximum units f vco vco frequency 2400 2500 mhz f pfd phase / frequency detector frequency 5200mhz f out output frequency qa[0:3] nqa[0:3] qb[0:3] nqb[0:3] qc[0:1] nqc[0:1] 10.91 2500 mhz qd0, nqd0 integer divider selected 10.91 2500 mhz fractional divider selected 20 250 mhz qd1 integer divider selected 10.91 250 mhz fractional divider selected 20 250 mhz t sk(b) bank skew d, e, f d. defined as skew between outputs at the same supply voltage and with equal load conditions. meas ured at the output differential crosspoints . e. this parameter is defined in accordance with jedec standard 65. f. this parameter is guaranteed by characterization. not tested in production bank a same frequency and output type only valid for skew between outputs in the same bank 45 ps bank b 45 bank c 20 t r / t f output rise/fall time qa[0:3] nqa[0:3] qb[0:3] nqb[0:3] qc[0:1] nqc[0:1] 30% to 70% 30 60 110 ps qd0, nqd0 30% to 70% 30 90 200 qd1 30% to 70% 220 375 600 odc output duty cycle g g. duty cycle of bypassed signals (input reference clock or crystal input) is not adjusted by the device. qa[0:3] nqa[0:3] qb[0:3] nqb[0:3] qc[0:1] nqc[0:1], qd0, nqd0 f out ? 1250mhz 45 50 55 % f out > 1250mhz 40 50 60 % qd1 f out < 156.25mhz 45 50 55 % f out ? 156.25mhz 40 50 60 % t lock pll lock time h h. pll lock time is defined as time from input clock availability to frequency locked output. the following loop filter compone nt values may be used: r z = 221 , c z = 4.7 f c p = 30pf. refer to applications information . 40 100 ms 34 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet table 29: qmn a and qd1 phase noise and jitter characteristics, v cc_x b = v ccox c = 3.3v+5%, t a = -40c to +85c d , e , f , g , h , i a. in this table, qmn denotes the differential outputs qa[0:3], qb[0:3], qc[0:1] or qd0. note that qd1 is not included because it is not differential. b. v cc_x denotes v cc_cp, v cc_ck, v cc_sp. c. v ccox denotes v ccoa, v ccob, v ccoc, v ccod. d. electrical parameters are guaranteed over the specified ambi ent operating temperature range, which is established when the d evice is mounted in a test socket with main- tained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. e. all outputs enabled and configured for the same output frequency unless otherwise noted. f. characterized using a 50mhz, c l = 18pf crystal, unless otherwise noted. g. measured on qmn configured as 16 and 20. h. v cca requires a voltage regulator. voltage supplied to v cca should be derived from a regulator with a typical power supply rejection ratio of 80db at 1khz and ultra low noise generation with a typical value of 3nv/ ? hz at 10khz and 7nv/ ? hz at 1khz. i. characterized with 750mv output voltage swing configuration for all differential outputs. symbol parameter test conditio ns minimum typical maximum units t jit(?) j j. the following loop filter component values were used: r z = 221 ? , c z = 4.7f, cp = 30pf. pll charge pump current control set at 5.2ma. rms phase jitter random qmn = 156.25mhz k k. characterized using a 31.25mhz, c l = 18pf crystal, (fox p/n fx277lf-31.25-1). integration range: 12khz ? 20mhz 87 110 fs rms phase jitter random qmn = 125mhz integration range: 12khz ? 20mhz 84 fs rms phase jitter random qmn = 100mhz integration range: 12khz ? 20mhz 94 fs rms phase jitter random qmn = 25mhz integration range: 12khz ? 5mhz 126 fs rms phase jitter random qd0 = 133.33mhz (fractional) l integration range: 12khz ? 20mhz 180 fs rms phase jitter random qd1= 125mhz integration range: 12khz ? 20mhz 170 fs rms phase jitter random m qan = 125mhz integration range: 12khz ? 20mhz 85 fs qbn = 100mhz integration range: 12khz ? 20mhz 88 fs qcn = 25mhz integration range: 12khz ? 5mhz 137 fs qd0 = 133.33mhz (fractional) integration range: 12khz ? 20mhz 170 fs ? n (10) n single-side band noise power, 10hz from carrier qmn = 156.25mhz -75.1 dbc/hz ? n (100) n single-side band noise power, 100hz from carrier qmn = 156.25mhz -109.6 dbc/hz ? n (1k) n single-side band noise power, 1khz from carrier qmn = 156.25mhz -128.9 dbc/hz ? n (10k) n single-side band noise power, 10khz from carrier qmn = 156.25mhz -137.6 dbc/hz ? n (100k) n single-side band noise power, 100khz from carrier qmn = 156.25mhz -143.0 dbc/hz ? n (1m) n single-side band noise power, 1mhz from carrier qmn = 156.25mhz -157.5 dbc/hz ? n (10m) n single-side band noise power, 10mhz from carrier qmn = 156.25mhz -163.1 dbc/hz ? n ( ? ) n noise floor ( ? 30mhz from carrier) qmn = 156.25mhz -163.1 dbc/hz 35 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet l. qax = 156.25mhz, qbx = 156.25mhz, qcx = 156.25mhz. m. qax = 156.25mhz, qbx = 100mhz, qcx = 25mhz, qd0 = 133.33mhz (fractional). n. measured using a 50mhz, 12pf crystal as input reference. the following loop filter components were used: r z = 150 ? , c z = 0.1f, cp = 200pf. pll charge pump current control set at 6.4ma. 36 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet typical phase noise at 156.25mhz a a: measured using a 50mhz, 12pf crystal as input reference. the following loop filter components were used: r z = 150 ? , c z = 0.1f, cp = 200pf. pll charge pump current control set at 6.4ma. noise power dbc offset frequency (hz) 37 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet typical phase noise at 125mhz a a. measured using a 50mhz, 12pf crystal as input reference. the following loop filter components were used: r z = 150 ? , c z = 0.1f, cp = 200pf. pll charge pump current control set at 6.4ma. noise power dbc offset frequency (hz) 38 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet applications information recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullup and/or pulldown resistors; additional resistance is not required but can be added for add itional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl outputs should be left floating. it is recommended that there is no trace attached. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating there should be no trace attached. lvcmos outputs qd1 output can be left floating if unused. there should be no trace attached. 39 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet overdriving the xtal interface the osci input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the osco pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be le ss than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent s ignal interference with the power rail and to reduce internal noise. figure 3 shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (r s) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 4 shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the osci input. it is recommended that all components in the schematics be plac ed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 3: general diagram for lvcmos driver to xtal input interface figure 4: general diagram for lvpecl driver to xtal input interface lvcmos_driver zo = 50 rs zo = ro + rs ro r2 100 r1 100 vcc osco osci c1 0.1 f lvpecl_driver zo = 50 r2 50 r3 50 c2 0.1 f osco osci zo = 50 r1 50 40 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet wiring the differential input to accept single-ended levels figure 5 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the inpu t will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impeda nce. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even thou gh the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specif ies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larg er, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. suggested edge rate faster than 1v/ns. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 5: recommended schematic for wiring a differential input to accept single-ended levels 41 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet 3.3v differential clock input interface clk/nclk accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 6 to figure 10 show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 6 , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termi nation recommendation. figure 6: clk/nclk input driven by an idt open emitter lvhstl driver figure 7: clk/nclk input driven by a 3.3v lvpecl driver figure 8: clk/nclk input driven by a 3.3v hcsl driver figure 9: clk/nclk input driven by a 3.3v lvpecl driver figure 10: clk/nclk input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input hcsl *r3 *r4 clk nclk 3.3v 3.3v differential input 42 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds co mpliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 11 can be used with either type of output structure. figure 12 , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termina tion, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since the se outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the outpu t. refer to figure 13 , figure 14 and figure 15 for additional details on the recommended termination schemes. figure 11: standard lvds termination figure 12: optional lvds termination lvds driver z o ? z t z t lvds receiver lvds driver z o ? z t lvds receiver c z t 2 z t 2 43 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet figure 13: dc termination for lvds outputs figure 14: ac termination for lvds outputs figure 15: ac termination for lvds outputs used with an input clock receiver with internal 50 ? terminations and dc bias. z0 = 50 z0 = 50 100 3.3v 3.3v 8v 9n 3 0 2 receiver input high impedance z0 = 50 z0 = 50 3.3v 3.3v 0.1f 8v 9n 3 2 receiver 0.1f internal 50 terminations 44 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are reco mmended only as guidelines.the differential outputs generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc curren t path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figure 16 and figure 17 show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee c ompatibility across all printed circuit and clock component process variations. figure 16: 3.3v lvpecl output termination figure 17: 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? inp ut 3.3v 3 .3v + _ 45 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorpora ted on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 18 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board thro ugh a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern m ust be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application sp ecific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved w hen an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surfac e mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 18: p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via 46 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet schematic layout figure 19 shows an example 8V49NS0312 application schematic operating the device at v cc = 3.3v. this example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure th at the logic control inputs are properly set for the application. to demonstrate the range of output stage configurations possible, the application schematic assumes that the 8V49NS0312 is prog rammed over i 2 c. for alternative dc coupled lvpecl options please see idt application note, an-828; for ac coupling options use idt applicati on note, an-844. for a 12pf parallel resonant crystal, tuning capacitors c145 and c146 are recommended for frequency accuracy. depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. crystal s with other load capacitance specifications can be used. this will require adjusting c145 and c146. for this device, the crystal tuning capacito rs are required for proper operation. crystal layout is very important to minimize capacitive coupling between the crystal pads and leads and other metal in the circ uit board. capacitive coupling to other conductors has two adverse effects; it reduces the oscillator frequency leaving less tuning margin and noise coupling from power planes and logic transitions on signal traces can pull the phase of the crystal resonance, inducing jitter. routing i 2 c under the crystal is a very common layout error, based on the assumption that it is a low frequency signal and will not affect the cr ystal oscillation. in fact, i 2 c transition times are short enough to capacitively couple into the crystal-oscillator loop if they are routed close enough to the crystal traces. in layout, all capacitive coupling to the crystal from any signal trace is to be minimized, that is to the osci and osco pins, traces to the crystal pads, the crystal pads and the tuning capacitors. using a crystal on the top layer as an example, void all signal and power lay ers under the crystal connections between the top layer and the ground plane used by the 8V49NS0312. then calculate the parasitic capacity to the ground and determine if it is large enough to preclude tuning the oscillator. if the coupling is excessive, particularly if the first layer under the crystal is a ground plane, a layout option is to void the ground plane and all deeper layers until the next ground plane is reached. the g round connection of the tuning capacitors should first be made between the capacitors on the top layer, then a single ground via is dropped to c onnect the tuning cap ground to the ground plane as close to the 8V49NS0312 as possible as shown in the schematic. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor mance, power supply isolation is required. the 8V49NS0312 provides separate power supplies to isolate any high switching noise from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. the ferrite bead and the 0.1uf capacitor in each power pin filter should always be plac ed on the device side of the board. the other components can be on the opposite side of the pcb if space on the top side is limited. pull up and pull down resistors to set configuration pins can all be placed on the pcb side opposite the device side to free up device side area if n ecessary. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devic es. depending on the application, the filter may need to be adjusted to get a lower cutoff frequency to adequately attenuate low-frequency no ise. additionally, good general design practices for power plane voltage stability suggest adding bulk capacitance in the local area of all device s. for additional layout recommendations and guidelines, contact clocks@idt.com. 47 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet figure 19: 8V49NS0312 application schematic 48 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet power dissipation and thermal considerations the 8V49NS0312 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. sin ce this device is highly programmable with a broad range of features and functionality, the power cons umption will vary as each of these featu res and functions is enabled. the 8V49NS0312 device was designed and characterized to operate within the ambient industrial temp erature range of -40c to +85 c. the ambient temperature represents t he temperature around the device, no t the junction temperature. wh en using the device in extrem e cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe a nd reliable junction temperature. extreme care must be taken to avoid exceeding 125c junction temperature. the power calculation examples below were generated using a ma ximum ambient temperature and supply voltage. for many applicatio ns, the power consumption will be much lower. please contact idt tech nical support for any concerns on calculating the power dissip ation for your own specific configuration. 49 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet example 1. lvpecl, 750mv output swing this section provides information on power dissipation and junction temperature when the device differential outputs are config ured for lvpecl level, 750mv output swing. equations and example calculations are also provided. 1a. power dissipation. the total power dissipation is the sum of the core power plus the power dissipated due to output loading. the following is the power dissipation for v cc = 3.465v, which gives worst case results. ? power(core) max = v cc_max * i ee_max = 3.465v * 497ma = 1722.1mw ? power(lvpecl outputs) max = 34.2mw/loaded output pair. refer to section 1c . if all outputs are loaded, the total power is 11 * 34.2mw = 376.2mw ? power (lvcmos output) max (power dissipation due to loading 50 ? to v cco / 2) output current: i out = v ccod_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 30 ? )] = 21.66ma power dissipation on the r out : power (r out ) = r out * (i out ) 2 = 30 ? * (21.66ma) 2 = 14.07mw ? total power max = power(core) + power (lvpecl outputs) + power (lvcmos output) = 1722.1mw + 376.2mw +14.07mw = 2112.37mw = 2.112w 1b. junction temperature. junction temperature, t j , is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, t j , to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for t j is as follows: t j = t a + p d * ? ja : t j = junction temperature t a = ambient temperature p d = power dissipation (w) in desired operating configuration ? ja = junction-to-ambient thermal resistance in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance must be used. assuming no ai r flow and a multi-layer board, the appropriate value is 15.6c/w per table 32 . therefore, assuming t a = 85c and all outputs switching, t j will be: 85c + 2.112w * 15.6c/w = 117.95c. this is below the limit of 125c. this calculation is only an example. t j will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 30: power calculations configuration #1 output output style output swing qa0 lvpecl 750mv qa1 lvpecl 750mv qa2 lvpecl 750mv qa3 lvpecl 750mv qb0 lvpecl 750mv qb1 lvpecl 750mv qb2 lvpecl 750mv qb3 lvpecl 750mv qc0 lvpecl 750mv qc1 lvpecl 750mv qd0 lvpecl 750mv qd1 lvcmos n/a 50 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet 1c. power dissipation due to output loading. the purpose of this section is to calculate the power dissipation for the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 20 . figure 20: lvpecl driver circuit and termination to calculate worst case power dissipation at the output(s), use the following equations which assume a 50 ? load, and a termination voltage of v ccox - 2v. these are typical calculations. ? for logic high, v out = v oh_max = v ccox_max - 0.8v (v ccox_max - v oh_max ) = 0.8v ? for logic low, v out = v ol_max = v ccox_max - 1.5v (v ccox_max - v ol_max ) = 1.5v pd_h is the power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v ccox_max ? 2v))/r l ] * (v ccox_max ? v oh_max ) = [(2v ? (v ccox_max ? v oh_max ))/r l ] * (v ccox_max ? v oh_max ) = [(2v ? 0.8v)/50 ? ] * 0.8v = 19.2mw pd_l = [(v ol_max ? (v ccox_max ? 2v))/r l ] * (v ccox_max ? v ol_max ) = [(2v ? (v ccox_max ? v ol_max ))/r l ] * (v ccox_max ? v ol_max ) = [(2v ? 1.5v)/50 ? ] * 1.5v = 15mw total power dissipation per output pair = pd_h + pd_l = 34.2mw v out v cco v cco - 2v q1 rl 50 51 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet example 2. lvds, 350mv output swing this section provides information on power dissipation and junction temperature when the device differential outputs are config ured for lvds levels, 350mv output swing. equations and example calculations are also provided. 2a. power dissipation. the total power dissipation is the sum of the core power plus the power dissipation due to output loading. the following is the power dissipation for v ccx = v cca_x = v ccox = 3.3v + 5% = 3.465v, which gives worst case results. ? power max = v ccx_max * i ccx_max + v cca_x_max * i cca_x_max + v ccox_max * i ccox_max = 3.465v * 100ma + 3.465v * 167ma + 3.465v (103ma + 105ma + 67ma + 69ma) = 346.5mw + 578.66mw + 1191.96mw = 2117.12mw = 2.117w 2b. junction temperature. junction temperature, t j , is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, t j , to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for t j is as follows: t j = t a + p d * ? ja : t j = junction temperature t a = ambient temperature p d = power dissipation (w) in desired operating configuration ? ja = junction-to-ambient thermal resistance in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance must be used. assuming no ai r flow and a multi-layer board, the appropriate value is 15.6 c/w per table 32 . therefore, assuming t a = 85c and all outputs switching, t j will be: 85c + 2.117w * 15.6c/w = 118.03 c. this is below the limit of 125c. this calculation is only an example. t j will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 31: power calculations configuration #2 output output style output swing qa0 lvds 350mv qa1 lvds 350mv qa2 lvds 350mv qa3 lvds 350mv qb0 lvds 350mv qb1 lvds 350mv qb2 lvds 350mv qb3 lvds 350mv qc0 lvds 350mv qc1 lvds 350mv qd0 lvds 350mv qd1 lvcmos n/a 52 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet reliability information table 32: thermal resistance table for 64-pin vfqfn package transistor count the transistor count for the 8V49NS0312 is: 143,063 symbol thermal parameter condition value unit ? ja a a. theta j a ( ? ja ) values calculated using an 8-layer pcb (114.3mm x 101.6mm), with 2oz. (70m) copper plating on all 8 layers, with epad connected to 4 ground planes. junction-to-ambient no air flow 15.6 c/w ? jc junction-to-case 15.3 c/w ? jb junction-to-board 0.6 c/w 53 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet 64-pin vfqfn package outline 54 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet 64-pin vfqfn package outline (continued) 55 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet ordering information part/order number marking package shipping packaging temperature 8V49NS0312nlgi idt8V49NS0312nlgi 64-pin vfqfn, lead-free tray -40c to +85c 8V49NS0312nlgi8 idt8V49NS0312nlgi 64-pin vfqfn, lead-free tape & reel -40c to +85c 56 ?2016 integrated device technology, inc. september 2, 2016 8V49NS0312 datasheet revision history revision date description of change september 2, 2016 page 32, table 27 crystal characteristics - added additional spec to equivalent series resistance row. august 1, 2016 page 50, power dissipation due to output loading. - typographical error replaced ?-? with ?=?: for logic low, v out = v ol_max = v ccox_max - 1.5v, (v ccox_max - v ol_max ) = 1.5v. july 11, 2016 initial release. disclaimer integrated device technology, in c. (idt) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of idt's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not conv ey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . copyright ?2016 integrated device tec hnology, inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com 8V49NS0312 datasheet |
Price & Availability of 8V49NS0312
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |